1. Field of the Invention
The present invention generally relates to semiconductor fabrication and more particularly to methods for forming multi-gate devices and the multi-gate devices made thereof.
More specifically, this invention relates to methods for forming multi-gate devices with improved carrier mobility.
2. Description of the Related Technology
Scaling down of silicon MOS devices has become a major challenge in the semiconductor industry. Whereas at the beginning, device geometrical shrinking already gave a lot of improvements in IC performance, nowadays new techniques, methods, materials and device architectures have to be introduced beyond the 90 nm technology node.
One major problem when scaling conventional planar devices are the short channel effects which start to dominate over the device performance. A solution for this problem came with the introduction of the multi-gate field effect transistor (MUGFET), also often referred to as fin-based semiconductor device or FINFET. Due to their three dimensional architecture, with the gate being wrapped around a thin semiconductor fin, an improved gate control (and thus less short channel effects) over the channel could be achieved by using multiple gates.
However, the introduction of this new device architecture has caused new problems. One of them is the insufficient mobility of the carriers in the device. The integration of a multi-gate pMOSFET (also referred to as pFINFET) and a multi-gate nMOSFET (also referred to as nFINFET) on one wafer is not straightforward, due to the fact that the mobility of electrons and holes occur preferentially along different crystal directions within the silicon crystal structure. Due to the parallel distribution of the pFINFET and the nFINFET on the wafer, i.e. both types of FINFET will be oriented along the same direction with respect to the crystal orientation of the wafer, either one of these two device types will not have the optimum channel direction and orientation, and hence will not have the optimum carrier mobility.
In case of silicon for example, the electron mobility is highest on a (100) substrate, with <110> channel direction (current direction), referred to as (100)/<110> orientation/direction or shortly (100)/<110>. The electron mobility is lowest on a (110) substrate, with <110> channel direction (current direction), referred to as (110)/<110> orientation/direction or shortly (110)/<110>. The hole mobility, however, is highest in the (110)/<110> orientation/direction, while it is lowest in the (100)/<110> orientation/direction.
For example in U.S. Patent Application US2004/0119100, pFINFET and nFINFET are made on the same substrate. The pFINFETs and nFINFETs for the multi-gate device are oriented at a first and second azimuthal angle respectively with respect to the axis orientation of the semiconductor wafer. The fin bodies of the pFINFET are thus oriented at an angle so that the resulting channel regions are along the {110} plane, while the fin bodies of the nFINFET are oriented at an angle so that the resulting channel regions are along the {100} plane. In silicon the {100} and {110} planes are oriented at 45 degrees with respect to one another, such that the fin bodies are likewise oriented at 45 degrees with respect to one another. However the enhancement in mobility is at the expense of the layout efficiency. Also manufacturing cost is increased due to the design complexity.
Additionally, in case of a multi-gate device, the top surface and sidewall surfaces orientation/direction play an important role for the mobility of the device. In case of a multi-gate device fabricated on a standard SOI (Silicon On Insulator) substrate with (100)/<110> orientation/direction, the top surface of the fin has (100)/<110> orientation/direction, while the sidewall surfaces of the fin have (110)/<110> orientation/direction. Therefore, it is beneficial to shape the nFINFET small and broad in order to maximize the top surface area and to shape the pFINFET tall and narrow to maximize the sidewall surfaces area. Hence, when using one substrate with one crystallographic orientation, a different geometry of n-type and p-type MUGFETs is required if the mobility of electron and holes is to be optimized simultaneously.
Although already some possibilities are available in the state-of-the-art for enhancing the mobility in multi-gate semiconductor devices, there is a need for other mobility enhancement techniques for multi-gate devices combine both an increased mobility for the p-type and the n-type MUGFET.